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Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
Converting each to binary representation results in the
following:
N register = 86 = 0101,0110
F register value =
0000,1110,0110,0110,0110,0110,0110
The F-register value is then split between an upper 14
bits and a lower 14 bits as follows:
Upper 14 bits + address 00 = 0000,1110,0110,0100
Lower 14 bits + address 01 = 1001,1001,1001,1001
Synthesizer Shutdown
The synthesizer can be disabled by setting SYNEN (pin
12) to a logic low. This mode is useful when an external
frequency synthesizer is employed.
Applications Information
Serial Interface and Register Definition
3-Wire Interface and Registers
The MAX2150 is programmed through a simple
3-wire (CLK, DATA, EN ) interface. The programming
data is contained within 16-bit words loaded into four
unique address locations. Each location contains pro-
gramming information for setting operational modes
and device configuration. Two words (address 00, 01)
control the fractional divide number in the sigma-delta
synthesizer. The third word (address 10) sets the inte-
ger divide value, reference divide value, charge-pump
current, and charge-pump compensation DAC settings.
The fourth and final word (address 11) contains various
device configuration registers and test registers, as
well as additional charge-pump compensation regis-
ters. See Tables 1 through 11 for details.
3-Wire Interface Timing Diagram
Figure 1 shows the programming logic. The 16-bit shift
register is programmed by clocking in data at the rising
edge of CLK. Pulling enable low allows data to be
clocked into the shift register; pulling enable high loads
the register addressed.
Fractional Spurs
When synthesizing a frequency that is an integer multi-
ple of the reference divider and having a fractional off-
set with a value less than the PLL filter bandwidth,
fractional spurs can be observed at a typical level of
-40dBc. For example, to synthesize 1640.005MHz
when using a 20MHz reference and a PLL bandwidth of
25kHz, spurious products offset from the LO by 5kHz
can be observed. The 1640MHz is an integer multiple
of 20MHz, and the fractional offset of 5kHz is within the
PLL bandwidth.
It is possible to avoid the above-mentioned spurious
products by using two reference oscillators with slightly
offset frequencies or by using a higher reference fre-
quency and changing the comparison frequency of the
reference divider.
Crystal Oscillator
The MAX2150 includes a simple-to-use on-chip low-
noise reference oscillator circuit. The oscillator is
formed by connecting a fundamental mode parallel res-
onant crystal from OSCIN to ground. The oscillator cir-
cuit is useful from 10MHz to 50MHz.
The phase noise of the MAX2150 can be improved by
using a precision high-frequency external reference
oscillator (TCXO). The external oscillator is connected
through a DC-blocking capacitor directly to the OSCIN
pin.
Layout Considerations
A properly designed PC board is an essential part of
any RF circuit. A ground plane is essential. Keep RF
signal lines as short as possible to reduce losses, radi-
ation, and inductance. The exposed pad on the under-
side of the MAX2150 must be adequately grounded by
ensuring that the exposed paddle of the device pack-
age is soldered evenly to the board ground plane. Use
multiple, low-inductance vias to ground the exposed
paddle.
DATA
B19 (MSB)
B18
B0
A3
A1
A0 (LSB)
t CS > 50ns
t CH > 10ns
t CWH > 50ns
CLK
t CWL
t ES > 50ns
t CWL > 50ns
t EW > 50ns
t CS
t CH
t CWH
t ES
EN
t EW
Figure 1. 3-Wire Interface Timing Diagram
10
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